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| MC74AC4040 12-Stage Binary Ripple Counter The MC74AC4040 consists of 12 master-slave flip-flops. The output of each flip-flop feeds the next and the frequency at each output is half that of the preceding one. The state of the counter advances on the negative-going edge of the Clock input. Reset is asynchronous and active-high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the MC74AC4040 for some designs. Features http://onsemi.com 16 1 PDIP-16 N SUFFIX CASE 648 * * * * * 140 MHz Typ. Clock Outputs Source/Sink 24 mA Operating Voltage Range: 2.0 to 6.0 V High Noise Immunity Pb-Free Packages are Available VCC 16 Q11 15 Q10 14 Q8 13 Q9 12 RESET CLK 11 10 Q1 9 16 1 SOIC-16 D SUFFIX CASE 751B 16 1 SOEIAJ-16 M SUFFIX CASE 966 ORDERING INFORMATION Device MC74AC4040N 1 Q12 2 Q6 3 Q5 4 Q7 5 Q4 6 Q3 7 Q2 8 GND MC74AC4040D MC74AC4040DG MC74AC4040DR2 Output State No Change Advance to next state All Outputs are low MC74AC4040M MC74AC4040DR2G MC74AC4040NG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 Shipping 25 Units/Rail 25 Units/Rail 48 Units/Rail 48 Units/Rail 2500 Tape & Reel Figure 1. Pinout: 16-Lead Packages Conductors (Top View) FUNCTION TABLE Clock Reset L L X H SOIC-16 2500 Tape & Reel (Pb-Free) SOEIAJ-16 50 Units/Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 4 of this data sheet. (c) Semiconductor Components Industries, LLC, 2006 1 November, 2006 - Rev. 7 Publication Order Number: MC74AC4040/D MC74AC4040 9 7 6 5 CLOCK 10 3 2 4 13 12 14 15 1 RESET 11 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 PIN 16 = VCC PIN 8 = GND Figure 2. Logic Diagram MAXIMUM RATINGS Symbol VCC VIN VOUT IIN IOUT ICC PD DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC VCC or GND Current per Output Pin Power Dissipation in Still Air Plastic{ SOIC Package{ Storage Temperature Lead Temperature, 1 mm from Case for 10 seconds (Plastic DIP or SOIC Package) Parameter Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 750 500 -65 to +150 260 C C Unit V V V mA mA mA mW Tstg TL Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating: Plastic DIP: - 10mW/C from 65C to 125C SOIC Package: -7.0 mW/C from 65C to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN/VOUT TA tr/tf DC Supply Voltage (Referenced to GND) Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise/Fall Time (Figure 1) VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V Parameter Min 2.0 0 -40 0 0 0 Max 6.0 VCC +85 150 40 25 Unit V - C ns/V http://onsemi.com 2 MC74AC4040 DC CHARACTERISTICS (unless otherwise specified) Symbol ICC Parameter Maximum Quiescent Supply Voltage Value 80 Unit mA Vin = VCC or GND VCC = 5.5 V, TA = Worst Case Vin = VCC or GND VCC = 5.5 V, TA = 25C ICC Maximum Quiescent Supply Current 8.0 mA DC CHARACTERISTICS 74AC VCC Symbol VIH Parameter Minimum High Level Input Voltage (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOLD IOHD Maximum Input Leakage Current Minimum Dynamic Output Current{ 5.5 5.5 5.5 TA = +25C Typ - - - - - - 2.99 4.49 5.49 - - - 0.002 0.001 0.001 - - - - - - 74AC TA = -40C to +85C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 - - 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 75 -75 Unit V Conditions VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 mA V *VIN = VIL or VIH -12 mA IOH -24 mA -24 mA IOUT = 50 mA V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA VI = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIL Maximum Low Level Input Voltage V VOH Minimum High Level Output Voltage V V mA mA mA *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. http://onsemi.com 3 MC74AC4040 AC CHARACTERISTICS (For Figures and Waveforms - See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) 74AC TA = +25C VCC* Symbol fmax nCP to Q1 Qn to Qn +1 MR to Q tHL trec nCP to MR tw nCP tw MR Parameter Maximum Clock Frequency Propagation Delay nCP to Q1 Propagation Delay Qn to Qn +1 Propagation Delay MR to Q Recovery Time Minimum Pulse Width Clock Pin Minimum Pulse Width Master Reset (V) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 3.0 Min 110 130 2.0 2.0 0 0 3.0 3.0 0 0 4.0 3.0 4.0 3.0 CL = 50 pF Typ 120 140 - - - - - - -2.5 -1.5 3.5 2.5 3.5 2.5 Max - - 11 8.0 5.5 3.5 12 10 - - - - - - 74AC TA = -40C to +85C CL = 50 pF Min 100 120 2.0 2.0 0 0 3.0 3.0 0 0 4.5 3.5 4.5 3.5 Max - - 14 10 6.5 4.5 15 12 - - - - - - Unit MHz ns ns ns ns ns ns Fig. No. - - - - - - - *Voltage Range 3.3 V is 3.3 V 0.3 V. *Voltage Range 5.0 V is 5.0 V 0.5 V. CAPACITANCE Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Value Typ 4.5 50 Unit pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V MARKING DIAGRAMS PDIP-16 MC74AC4040N AWLYYWWG SOIC-16 AC4040G AWLYWW SOEIAJ-16 74AC4040 ALYW A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package http://onsemi.com 4 MC74AC4040 PACKAGE DIMENSIONS PDIP-16 CASE 648-08 ISSUE T -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 STYLE 1: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. CATHODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE 15. ANODE 16. ANODE STYLE 2: PIN 1. COMMON DRAIN 2. COMMON DRAIN 3. COMMON DRAIN 4. COMMON DRAIN 5. COMMON DRAIN 6. COMMON DRAIN 7. COMMON DRAIN 8. COMMON DRAIN 9. GATE 10. SOURCE 11. GATE 12. SOURCE 13. GATE 14. SOURCE 15. GATE 16. SOURCE SOIC CASE 751B-05 ISSUE J -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S http://onsemi.com 5 MC74AC4040 PACKAGE DIMENSIONS SOEIAJ-16 CASE 966-01 ISSUE A 16 9 LE Q1 E HE M_ L DETAIL P 1 8 Z D e A VIEW P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). c b 0.13 (0.005) M A1 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 6 MC74AC4040/D |
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